1. Field of the Invention
The invention relates to the fabrication of multilevel electrical interconnects, and more particularly to a method of forming via holes between the top of a dielectric layer and various levels of underlying metallization prior to filling the via holes with a conductive material.
2. Description of Related Art
Current multi-chip circuitry design requires the attachment of numerous integrated circuit chips to high density electrical interconnects, also known as high density multi-chip-modules (MCMs) or as substrates. Substrates normally include surface pads for bonding to surface mounted chips, a dielectric, and electrical lines buried in the dielectric for connecting selected pads to provide electrical routing between various bond sites on the chips. It is common to use copper for the buried lines and a polymer such as polyimide for the dielectric. The copper lines may form separate layers of orthogonal wiring sets. It then becomes necessary to interconnect the copper lines to each other and/or the surface pads. This can be done by either staggered or stacked metallization (or metal vias). Staggered via designs normally result in lower interconnect density than stacked vias. Stacked vias, such as vertical metal pillars residing in vertical via holes, may be built either additively or subtractively. Additive construction involves building up pillars over an underlying base and depositing dielectric around the pillars. The subtractive approach, to which the present invention is directed, works in the opposite direction. Via holes are formed or etched in a dielectric and metal is deposited in the via holes.
Needless to say, one of the most important factors in the viability of any high density multilayer substrate is fabrication cost. Cost is roughly determined by the number of fabrication steps. More fabrication steps typically increase labor and material costs as well as decrease yields. Thus, any mature process which reduces the number of steps required to produce an equivalent substrate is useful and valuable.
Other methods have been developed in order to efficiently form via holes in a dielectric. The main thrust has been layer-by-layer. That is, for each layer with a dielectric over metal lines, via holes are formed in that layer before the next layer is constructed. In this manner, a separate step for forming via holes becomes necessary for each layer. See Levinson et al., "High Density Interconnects Using Laser Lithography," ISHM '88 Proc., 1988, pp. 301-306; and U.S. Pat. No. 4,897,153 to Cole et al. For instance, fabricating a four layer substrate (with a power plane, ground plane, X-conductors and Y-conductors) normally requires four separate steps (one for each layer) just to form the via holes. Therefore, the related art does not teach how to reduce the number of steps required to form via holes in each layer of a multilayer structure as additional layers are added.